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Title: Semiconductor Industry Savior: Further Acceleration in Package Innovation Dr. Yun Tae Lee, Former CEO Samsung Electro-Mechanics Co., Ltd., Korea |
Abstract
TBD
Biography
Education
1994. Feb. (PH D) KAIST, Electrical Engineering
1985. Feb. (Master) KAIST, Electrical Engineering
1983. Feb. (Bachelor) Seoul National University, Electrical Engineering
Career
2020. Jan.~ Now Samsung Electro-Mechanics, Executive Advisor
2014. Dec.~ 2019. Dec. Samsung Electro-Mechanics, President/CEO
2012. Apr.~ 2014. Nov. Samsung Display, Head of LCD R&D (Executive VP)
2011. Dec.~ 2012. Mar. Samsung Electronics, Head of LCD R&D (Senior VP)
2006. Feb.~ 2009. Jan. Samsung Electronics Semiconductor S.LSI Div., Head of Product Planning Team (VP)
1985. Feb.~ Join Samsung Electronics
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Title: Next Generation Terabyte/s HBM (High-bandwidth Memory Module) Designs for Advanced Artificial Intelligence (AI) Servers Prof. Joungho Kim KAIST(Korea Advanced Institute of Science and Technology), Korea |
Abstract
Recently, we are facing a newly emerging technology and industrial transition, named as 4th Industrial Revolution, which is based on artificial intelligence (AI), big data platform, cloud computing, and metaverse system. Especially, emergence of artificial intelligence and machine learning is aided by availability of big data, deep learning algorithms, and high-performance GPU computing machines. Accordingly, demands for advanced performance of terabyte/s bandwidth computing performance are rapidly increasing. However, continuously growing gaps between GPU performance and DRAM I/O data bandwidth are becoming the critical barrier to limit the AI computing performance. In order to meet the pressing needs of higher data transfer bandwidth, we are proposing High Bandwidth Memory (HBM) solutions using TSV, Si interposer technologies, and stacked memory architectures.
In this presentation, we will introduce the advanced approaches and designs of the next generation terabyte/s bandwidth 2.5D HBM (High-bandwidth Memory Module), which will be critically needed for artificial intelligent servers and super computers. Especially, we will talk about the signal and power integrity design issues, and analysis results of TSV and Si interposer channels, including GPU-DRAM channels, and high-speed serial channels. In addition, we will discuss PDN (power Distribution Network) impedance designs, and decoupling capacitor schemes as well. We will also suggest new computer architectures including PIM-HBM and Integrated HBM foe hybrid and memory-based computing architectures to meet the increasing performance needs of AI serves with reduced power consumptions. Finally, we will demonstrate the Machine Learning based Design Methods (MLDB) for semiconductor, HBM, and package designs.
Biography
Dr. Joungho Kim received B.S. and M.S. degrees in electrical engineering from Seoul National University, Seoul, Korea, in 1984 and 1986, respectively, and Ph.D degree in electrical engineering from the University of Michigan, Ann Arbor, in 1993. In 1994, he joined Memory Division of Samsung Electronics, where he was engaged in Gbit-scale DRAM design. In 1996, he moved to KAIST (Korea Advanced Institute of Science and Technology). He is currently professor at electrical engineering department of KAIST and the joint faculty member of KAIST AI college. He serves as the director of Samsung Industry Collaboration Center.
Recently, his research is focusing on the developing Deep Reinforcement Learning Methods for the optimal design of high-speed channels and the delivery networks in HBM and AI computer modules. In addition, his research centers on signal integrity and power integrity modeling, design, and measurement methodologies for HBM, 3D IC, TSV, Interposer, and System-in-Packages. He has authored and co-authored over 588 technical papers published at refereed journals and conference proceedings. Also, he has given more than 267 invited talks and tutorials at the academia and the related industries. He is currently the director of Samsung-KAIST industrial Collaboration Center.
He published a book, “Electrical Design of Through Silicon Via,” by Springer in 2014. And he was the symposium chair of IEEE EDAPS Symposium 2008, and was the TPC chair of APEMC 2011. He was also an associated editor of the IEEE Transactions of Electromagnetic Compatibility. He received Outstanding Academic Achievement Faculty Award of KAIST in 2006, KAIST Grand Research Award in 2008, National 100 Best Project Award in 2009, KAIST International Collaboration Award in 2010, KAIST Grand Research Award in 2014, and Teaching Award in 2015, respectively. He was appointed as an IEEE EMC society distinguished lecturer in a period from 2009-2011. He received Technology Achievement Award from IEEE Electromagnetic Society in 2010. He is IEEE fellow.