|Title: Warpage after molding processes: Can we really predict this?
Prof. Bongtae Han
University of Maryland, USA
Residual stresses exist inherently in components encapsulated by molding processes. They are combined with the stresses caused by the CTE mismatch, and eventually dictate the final warpage of components at room and reflow temperatures. For the past couple of decades, extensive efforts have been made to enhance the predictability of warpage. On the modeling front, commercial software packages are equipped with advanced but user-friendly analysis modules. As a result, even non-experts can model/simulate almost any kind of electronic packaging products. On the experimental front, thermo-mechanical properties required for numerical predictions, including CTE, Tg, and the temperature-dependent viscoelastic properties, are routinely measured by commercial tools such as TMA and DMA. In addition, temperature-dependent warpage can be measured using commercial shadow Moiré and DIC tools, and the results are used for model validation. Then, why is it still difficult to make quantitative prediction of warpage after molding processes?
Some studies in the literature show excellent agreements between warpage measurements and predictions. Yet, even the verified model does not predict the warpage of different packages molded by the same EMC accurately. In fact, good agreements of warpage between predictions and measurements are possible even when the properties of EMC are not correct and/or some critical properties of EMC are missing.
This presentation discusses in detail the incorrect and missing properties for the current practice of warpage modeling, and presents novel experimental methods to measure the required properties.
Dr. Bongtae Han is Keystone Professor at the Mechanical Engineering Department of the University of Maryland. Dr. Han has co-authored a textbook entitled “High Sensitivity Moiré: Experimental Analysis for Mechanics and Materials”, Springer-Verlag (1997) and edited two books. He has published 13 book chapters and over 300 journal and conference papers in the field of microelectronics, photonics and experimental mechanics.
He was a recipient of the 2002 Society for Experimental Mechanics (SEM) Brewer Award for his contributions to development of photomechanics tools used in semiconductor packaging. He was named the 2015 American Society of Mechanical Engineering (ASME) Mechanics Award winner in Electronic and Photonic Packaging Division for his contributions to structural mechanics of electronic systems. His publication awards include (1) the Year 2004 Best Paper Award of the IEEE Transactions on Components and Packaging Technologies, (2) the Gold Award (best paper in the Analysis and Simulation session) of the 1st Samsung Technical Conference in 2004 and (3) the Year 2015 Best Paper Award of the 16th International Conference on Electronic Packaging Technology (ICEPT 2015). He served as an Associate Technical Editor for Experimental Mechanics, from 1999 to 2001; for Journal of Electronic Packaging, Transaction of the ASME from 2003 to 2012; for Microelectronics Reliability from 2017 to 2020. He is currently serving as a Co-Editor-in-Chief for Microelectronics Reliability.
He was elected Fellow of the SEM and the ASME in 2006 and 2007, respectively.
|Title: Advanced Packaging Technology & Materials trends
Dr. Santosh KUMAR
Yole Dévelopement, France
Semiconductor industry has entered a new age where mobile /consumer and other drivers like big data, artificial intelligence, 5G, high performance computing (HPC), AR/VR/MR, cloud/edge computing, IoTs (including industrial IoT), smart automotive, industry 4.0, hyperscale data centers is creating demand for system or subsystems which require high computing power, high speed, more bandwidth, low latency, low power, more functionality, more memory, system level integration, variety of sensors while keeping the cost low. Heterogeneous integration using AP technologies is key to fulfil these system performance requirements and increase the value of a semiconductor product, adding functionality, maintaining/increasing performance while lowering cost. This places immense pressure on package suppliers with an increasing degree of customization required for each individual customer. Advanced Packaging market was $30B in 2020 and is expected to grow at CAGR2020-2026 of ~8% to reach ~ $48B in 2026. The megatrend applications are fueling the next generation of advanced packaging platforms (high-density FOWLP, 3D stacked TSV memory, WLCSP, and flip-chip), which have reached a new level of complexity and now demand higher integration-level requirements. These lofty standards will strongly influence the increasing demand for advanced materials with new technical specifications, to achieve better performance. The presentation will discuss about the advanced packaging technology and related materials trends.
Santosh Kumar is currently working as Senior Director & Principal Analyst at Yole Développement. He is a technologist and strategist with a multifaceted experience in the materials, process and business development including industrial market & technology strategic analysis in the field of semiconductor packaging and manufacturing. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging. He worked on multiple projects with several multi-national companies covering entire microelectronics supply chain from fabless players, OEMs, IDMs, OSATs to equipment & material suppliers. He received the bachelor and master’s degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul, respectively. He has published more than 50 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.